This invention relates to a signal delay device a delay time of which can be controlled easily.
Known in the art of a signal delay circuit are various circuits such, for example, as a physical delay line, a distributed constant circuit, a bucket-brigade device (BBD), a charge-coupled device (CCD), and a shift register and a program control utilizing a random-access memory (RAM) in a digital system.
In various circuits to which a signal delay circuit is applied, there is a technical demand for arbitrarily varying a delay time of the delay circuit. Such arbitrary variation of the delay time can hardly be achieved by a delay line or a distributed constant circuit and, for this purpose, a bucket-brigade device, a charge-coupled device, a shift register or like device which uses a clock pulse for transmission of a signal is generally employed to control the frequency of the clock pulse.
In such delay system utilizing a clock pulse for transmission of a signal, a signal is sampled by a clock pulse and, accordingly, resolution of the system along the time axis is determined by the clock period. As a result, in a case where, for example, a pulse frequency modulation signal containing analog data along the time axis is to be delayed, a phase error tends to occur in the delay output. This defect can theoretically be eliminated by employing a very fast clock and thereby improving the resolution. This requires, however, increase in the number of stages of a delay element such as a bucket-brigade device, a charge-coupled device or a shift register with resulting difficulties in the circuit design and increase in the manufacturing costs.
It is, therefore, a first object of the invention to provide a signal delay device a delay time of which can be readily controlled without causing a phase error.
For achieving this object, the invention utilizes the phenomena that a CMOS gate has a delay time between its input and output terminals and this delay time changes depending upon voltage applied thereto.
The delay time of the CMOS gate depends upon power voltage and temperature. The smaller the power voltage, the longer the delay time and the larger the rate of change. As to the temperature, the higher the temperature, the longer the delay time. This is because conductance of the element of the CMOS gate changes due to the power voltage and temperature. Since dependency of the delay time upon the power voltage and temperature is too large to be ignored and influences of these factors are observed as instability in the oscillation period in an oscillation circuit and increase in distortion in the transmission system, it has been difficult to use the CMOS gate as a delay circuit in a circuit which requires a precision control. For overcoming such difficulty, it is conceivable to use a strictly stabilized power source and provide the CMOS gate in a thermostatic oven. This will however require a bulky and costly circuitry.
It is, therefore, a second object of the invention to provide a delay time stabilizing circuit capable of accurately stabilizing the delay time of the delay circuit utilizing the CMOS gate with a simple construction.
The above described delay circuit utilizing the CMOS gate is applicable to various circuits and devices. One of them is an analog delay circuit.
As described above, the prior art analog delay circuit using a bucket-brigade device, a charge-coupled device, a shift register or the like device uses a clock pulse for transmitting a signal. Since a signal is sampled by a clock pulse in this type of delay circuit, resolution in the time axis is determined by the clock period with a result that the distortion factor increases. Further, although the delay time can be changed by changing the clock period in this type of delay circuit, resolution also is caused to change with the change of the clock period.
It is, therefore, a third object of the invention to provide an analog delay circuit capable of delaying an analog signal with a high resolution and a low distortion factor and also capable of changing the delay time continuously without changing the resolution by employing the delay circuit using the CMOS gate.
The delay circuit utilizing the CMOS gate finds application also in a circuit for absorbing a jitter (i.e., sway along the time axis) which occurs in reproducing a signal recorded on a recording medium such as a disc or a tape.
In a case where a recorded signal is a pulse frequency modulation signal such as an FM signal of a video disc which takes a continuous value along the time axis, a jitter occurring in a reproduction mode due to instability of a drive system for the recording medium causes distortion or noise in demodulation. For preventing occurrence of such jitter, it is conventional to apply a servo control generally called a tangential control according to which the drive system or a pickup head itself is included in the servo loop. This system, however, requires a movable portion provided in the pickup head for performing the tangential control with a result that the construction of the pickup head becomes complicated. Besides, the tangential control requires a high speed response and therefore requires a construction of a small inertia. It is however difficult to realize a construction of a small inertia with such a complicated construction. The same is the case with a device using a tape as the recording medium such as a tape deck and a magnetic tape memory.
It is, therefore, a fourth object of the invention to provide a jitter absorption circuit employing the delay circuit utilizing the CMOS gate in a device for reproducing a recorded signal, the jitter absorption circuit being capable of absorbing a jitter without providing a device for absorbing jitter in the pickup head.
The delay circuit utilizing the CMOS gate is applicable also to a circuit for absorbing a jitter from a reproduced signal on a Compact Disc in the Compact Disc Digital Audio System.
In a Compact Disc, a jitter occurs during reproduction due to instability of the drive system and this causes wow and flutter. For preventing occurrence of jitter, a jitter absorption circuit is employed to effect correction along the time axis. This jitter absorption circuit includes a data processing memory which comprises an error correction region and a jitter absorption region. This jitter absorption region requires a large capacity so that it will be able to cope with a jitter of a large magnitude.
It is, therefore, a fifth object of the invention to provide a jitter absorption circuit which can obviate the jitter absorption memory or reduce the size thereof by employing the delay circuit utilizing the CMOS gate.
Still another application of the delay circuit utilizing the CMOS gate is a circuit for correcting a synchronizing error between signals reproduced from respective tracks due to azimuth deviation of a magnetic head in a fixed head type magnetic tape reproducing device such as a multiple track PCM tape recorder.
Azimuth deviation of a magnetic head in a magnetic tape reproducing device is difference between the angle of inclination of a recording head to the magnetic tape and the angle of inclination of a reproducing head to the magnetic tape. Gaps of the recording and reproducing heads are both designed to become normal to the running direction of the magnetic tape so that there will be no azimuth deviation. In actuality, however, azimuth deviation does occur, for in most cases the recording head is constructed separately from the reproducing head.
For correcting such azimuth deviation, a conventional method is to adjust the inclination of the magnetic heads strictly. This method necessitates individual adjustment for each device. Besides, this method cannot cope with irregularity in the recording heads. Another prior art method is to adjust azimuth automatically by slightly moving the magnetic heads. This method requires a very complicated movable mechanism in the magnetic heads.
It is, therefore, a sixth object of the invention to provide, by employing the delay circuit utilizing the CMOS gate, a fixed head type magnetic tape reproducing device capable of correcting a synchronizing error between signals reproduced from the respective tracks without performing adjustment of azimuth of the magnetic heads.